module pc(rst, clk, pc_en, pc_in, pc_out);

 input rst, clk;
 input pc_en;
 
 input[15:0] pc_in;

 output[15:0] pc_out;

 wire[15:0] d_in;

 dff d[15:0] ( .q(pc_out), .d(d_in), .clk(clk), .rst(rst));
 
 assign d_in = (pc_en)? pc_in : pc_out;
 

endmodule 
